A synchronizing signal separation circuit is generally used for separating the composite synchronizing signal from the composite video signal in a television receiver.
FIG. 1 shows a typical example of a conventional synchronizing pulse separation circuit, which can operate on a composite video signal obtained by a television receiver.
Referring now to FIG. 1, a circuit construction of the composite synchronizing signal separation circuit 10 will be described in detail hereafter. The composite synchronizing signal separation circuit 10 is provided with an input terminal 12 for receiving a composite video signal AV. The composite video signal AV is obtained from a tuner circuit (not shown in the drawing) of a television receiver.
The composite synchronizing signal separation circuit 10 includes three transistors 14, 16, and 18, two diodes 20 and 22, five resistors 24, 26, 28, 30, and 32, a capacitor (referred as a coupling capacitor hereafter) 34, a reference voltage source 36 and a constant current source 38. The reference voltage source 36 and the constant current source 38 provide a prescribed reference voltage E1 and a prescribed constant current I1, respectively.
The emitter of the transistor 14 is coupled to the input terminal 12 of the composite synchronizing signal separation circuit 10 in series through the first capacitor 34 and the resistor 24. Further, the emitter of the transistor 14 is coupled to a grounded terminal 40 through the constant current source 38. The base of the transistor 40 is coupled to the grounded terminal 40 through the reference voltage source 36. The collector of the transistor 14 is coupled in series to a power supply source line 42 through the diodes 20 and 22. Further, the collector of the transistor 14 is coupled to the base of the transistor 16.
The emitter of the transistor 16 is coupled to its base through the resistor 28. Further, the emitter of the transistor 16 is coupled to the power supply source line 42 through the resistor 26. The collector of the transistor 16 is coupled to the grounded terminal 40 through the resistor 30. Further, the collector of the transistor 16 is coupled to the base of the transistor 18.
The collector of the transistor 18 is coupled to the power supply source line 42. The emitter of the transistor 18 is coupled to the grounded terminal 40 through the resistor 32. Thus, the transistor 18 and the resistor 32 constitute an emitter follower circuit 44. The emitter of the transistor 18 is coupled to an output terminal 46 of the composite synchronizing signal separation circuit 10 for outputting the composite synchronizing signal CS.
The composite video signal AV is supplied to the emitter of the transistor 14 through the coupling capacitor 34 and the resistor 24, as described above. The coupling capacitor 34 and the resistor 24 constitute a series time constant circuit 48. The time constant T48 of the series time constant circuit 48 is defined by the resistance R24 of the resistor 24 and the capacitance C34 of the coupling capacitor 34 and is expressed by the equation: T48=R24.multidot.C34.
The composite video signal AV is required to have at least a prescribed threshold voltage Vth to cause the transistor 14 to conduct. The threshold voltage Vth is given by the following equation, provided that the time constant T48 is sufficiently larger than the horizontal line period Th of the horizontal signal. ##EQU1## wherein; Ts; Synchronizing signal period, and
I1; Current of the constant current source 38.
The equation (1) is changed as follows; ##EQU2##
When the transistor 14 is conductive, a current I14 expressed by [(Th-Ts)/Ts].multidot.I1 flows through the collector of the transistor 14. A partial current I28 of the current I14 flows through the resistors 26 and 28 so that the transistor 16 becomes conductive. As a result, the composite synchronizing signal CS is output from the emitter of the transistor 18. At this time, a clamp circuit 50 formed by the diodes 20 and 22 is activated, so that the base potential Vb16 of the transistor 16 is held at a value expressed as (Vcc-2.multidot.Vf) and the emitter current Ie16 of the transistor 16 is held at a value expressed as Vf/R28, where Vf is the forward voltage drop of the diodes, such as the diodes 20 and 22, and R28 is the resistance of the resistor 28.
As mentioned above, for obtaining the composite synchronizing signal CS from the emitter of the transistor 18, the partial current I28 flowing through the resistor 28 is required to be at least a value expressed by Vf/R28 to make the transistor 16 conductive. The partial current I28 depends on the conductivity of the transistor 14. Thus, the actual threshold voltage becomes smaller than the previous threshold value Vth. If the actual threshold voltage is assumed as Vth.multidot.a, the voltage Vth.multidot.a is given by the following equation: ##EQU3##
The composite synchronizing signal CS obtained on the emitter of the transistor 18 is supplied to the output terminal 46 through the emitter follower circuit 44. As a result, the composite synchronizing signal CS is output to the output terminal 46.
However, such a conventional synchronizing signal separation circuit 10 has a drawback. In the composite video signal AV, the peak voltage of the composite synchronizing signal component CS may suddenly change. If the composite video signal AV is the signal applied from a VTR (abbreviation of Video Tape Recorder), the composite video signal AV is processed an APL (abbreviation of Average Picture Level) control. The APL operation controls the composite video signal AV so that the positive and negative signal intensities of the signal AV are unified or averaged. As a result, the peak level of the composite synchronizing signal component CS often changes. Such a peak level change of the composite synchronizing signal component CS deteriorates the stability of the signal separating operation of the composite synchronizing signal separation circuit 10. As a result, the composite synchronizing signal component CS obtained by the composite synchronizing signal separation circuit 10 becomes unstable.
The above-mentioned problem can be solved if the response characteristics of the composite synchronizing signal separation circuit 10 for the composite video signal AV are improved. This is done by making the capacitance C34 of the coupling capacitor 34 small. However, reducing the capacitance C34 of the coupling capacitor 34 causes another problem in that the coupling capacitor 34 is still charged for the period of the vertical synchronizing signal component VS in the composite synchronizing signal CS.
The problem of the small capacitance C34.multidot.s of the coupling capacitor 34 will be briefly described in reference to FIG. 2. As shown in FIG. 2, the composite synchronizing signal CS includes horizontal synchronizing signals HS, equalizing signals ES and the vertical synchronizing signals VS. The equalizing signals ES and the vertical synchronizing signals VS are located in the vertical blanking period, as shown in the drawing. As is well known, the pulse widths of the horizontal synchronizing signals HS and the equalizing signals ES are as short as about 4.7 .mu.s and 2.5 .mu.s. On the other hand, the pulse width of each of the veritcal synchronizing signals VS is about 27 .mu.s which is extremely longer than those of the horizontal synchronizing signals HS and the equalizing signals ES, i.e., about 4.7 .mu.s and 2.5 .mu.s. The vertical synchronizing signals VS are serrated from each other by serrated pulses SP with pulse width of about 5 .mu.s. According to the above fact, the charge of the coupling capacitor 34 is accumulated without being sufficiently discharged in the period of the serrated pulses SP between the vertical synchronizing signals VS, when the capacitance C34 of the coupling capacitor 34 is small. As a result, the vertical synchronizing signals VS sag, as shown by the broken line graph in the drawing. When the sagging advances, the peak level of the vertical synchronizing signals VS or the equalizing signals ES exceeds the threshold level Vth of the transistor 14 (see FIG. 1). Thus, the emitter potential of the transistor 14 fluctuates in response to the charged potential of the capacitor 34. This causes the composite synchronizing signal CS and the vertical synchronizing signal VS to sag during the cycle of the vertical synchronizing signal VS. This also causes other problems, such as curving of horizontal images and deterioration of the stability of synchronization.